In recent semiconductor devices, to reduce power consumption the internal circuitry is designed to handle signals whose voltage level is lower than the signal level used outside the semiconductor device. That is, the supply voltage on which the internal circuitry is designed to operate is set lower than the signal level used outside the semiconductor device.
To achieve this, the input and output circuits of the semiconductor device are provided with a level converter for converting the signal level of the internal circuitry to the external signal level.
FIG. 1 is a circuit diagram illustrating one example of a prior art level converter.
The prior art level converter illustrated in FIG. 1 comprises a pair of cross-coupled p-channel MOS transistors (pMOS transistors) Tp1 and Tp2 and a pair of n-channel MOS transistors (nMOS transistors) Tn1 and Tn2 whose gates are supplied with complementary input signals.
The sources of the pMOS transistors Tp1 and Tp2 are connected to a high power supply line (AVD), and the drains of the pMOS transistors Tp1 and Tp2 are connected to the drains of the nMOS transistors Tn1 and Tn2 via nodes N1 and N2, respectively, while the sources of the nMOS transistors Tn1 and Tn2 are connected to a low power supply line (DVS).
Then, when the input signal, in or /in, supplied to the gate of either one of the nMOS transistors Tn1 and Tn2 goes to a high level “H”, for example, when the input signal, in, supplied to the gate of the nMOS transistor Tn1 goes to a high level “H”, and the input signal, /in, supplied to the gate of the nMOS transistor Tn2 goes to a low level “L”, the node N1 is held at the low level “L”, while on the other hand, the node N2 is held at the high level “H”.
The voltages at which the respective nodes are held are determined by the bias voltages AVD and DVS of the circuit, but need not be the same as the input gate voltages (in and /in) of the nMOS transistors Tn1 and Tn2, and these node voltages make signal level conversion possible. Here, the voltages held at the nodes N1 and N2 produce an output voltage which is usually higher than the input voltage.
While the pMOS transistors Tp1 and Tp2 and nMOS transistors Tn1 and Tn2 used in the level converter illustrated in FIG. 1 are all slow transistors having breakdown voltages matched to the output voltage side, the input voltages to the nMOS transistors Tn1 and Tn2 are held low.
Next, consider the case where the input signal, in, supplied to the gate of the nMOS transistor Tn1 makes a transition from the low level “L” to the high level “H” (the input signal, /in, supplied to the gate of the nMOS transistor Tn2 makes a transition from the high level “H” to the low level “L”).
In the initial state, the node N1 is at the high level “H”, and the node N2 is at the low level “L”. Therefore, the pMOS transistor Tp1 is ON.
Subsequently, when the input signal, in, makes a transition from the low level “L” to the high level “H”, the nMOS transistor Tn1 also turns ON, but since the nMOS transistor Tn2 and the pMOS transistor Tp2 are both OFF, the initial change of the circuit's internal state begins by gradually lowering the voltage at the node N1 as the nMOS transistor Tn1 overcomes the pMOS transistor Tp1.
When the voltage of the node N1 drops to a certain level (approximately equal to the threshold voltage of the pMOS transistors), the pMOS transistor Tp2 begins to turn ON, so that the potential at the node N2 gradually rises, causing the force of the pMOS transistor Tp1 to decrease, and thereafter, the state changes at an increasingly rapid pace.
Here, if the driving capabilities of the nMOS transistors are made smaller than those of the pMOS transistors, the initial change is slow, but the pace of changing state thereafter is rapid. Conversely, if the driving capabilities of the nMOS transistors are made larger than those of the pMOS transistors, the initial change is rapid, but the pace of changing state thereafter is slow. Therefore, the level converter of FIG. 1 cannot have a high speed operation characteristic. Furthermore, since the nMOS transistors are driven at a lower voltage, a further delay may be caused.
In view of the above, various improvements to the level converter illustrated in FIG. 1 have been proposed in the prior art.
Specifically, in one proposed level converter, to reduce the voltages applied to the drains of the nMOS differential transistor pair, nMOS transistors are connected in a cascode configuration between the cross-coupled pMOS transistor pair and the nMOS differential transistor pair so that the level converter can operate at a low supply voltage despite the presence of the high supply voltage (see, for example, Japanese Patent No. 2816124: FIG. 2).
There is also proposed in the prior art a level converter featuring a low current consumption and fast response; this level converter comprises a basic level shift circuit having the characteristic of being quick in falling but slow in rising, two additional transistors connected in parallel for accelerating the rising of the level shift circuit, and a signal change detection pulse generating circuit for generating a pulse by capturing the falling of a signal, wherein the acceleration transistors are operated by detecting the falling of one output signal and generating a pulse so as to accelerate the rising of the other output signal (see, for example, Japanese Laid-open Patent Publication No. 05-343980: FIG. 1).
The prior art further proposes a level converter that uses a current mirror circuit to achieve high speed operation while reducing the input signal voltages (see, for example, Japanese Laid-open Patent Publication No. 2005-033718: FIG. 3).
As earlier described, it has been difficult to achieve high speed operation with the prior art level converter described, for example, with reference to FIG. 1.
FIG. 2 is a circuit diagram illustrating another example of a prior art level converter, which is described in the above-cited patent document 1.
In the prior art level converter illustrated in FIG. 2, to reduce the voltages applied to the drains (nodes N1 and N2) of the nMOS transistors Tn1 and Tn2, nMOS cascode transistors Tn31 and Tn32 are connected between the nodes N1, N2 and the drains of the nMOS transistors Tn1 and Tn2, and core transistors capable of high speed operation with a low driving voltage are used as the nMOS transistors Tn1 and Tn2.
In FIG. 2, a resistor Rv and an nMOS transistor Tn33 are for generating a bias voltage Vb to be applied to the gates of the nMOS cascode transistors Tn31 and Tn32.
The prior art level converter illustrated in FIG. 2 is capable of high speed operation but has the problem that the power consumption increases because a steady-state current flows.
FIGS. 3A, 3B, and 3C are circuit diagrams illustrating a further example of a prior art level converter.
In the prior art level converter illustrated in FIG. 3A, the cross-coupled pMOS transistors Tp1 and Tp2 are formed from small (narrow gate width) transistors, and large (wide gate width) pMOS transistors Tp3 and Tp4 are provided in parallel with them.
Here, as illustrated in FIG. 3C, for example, the gate of the pMOS transistor Tp3 is supplied with a control signal CS1 having a prescribed delay and pulse width, created through inverters I21 to I24 and a NAND gate 2 by taking the signal of the node N2 as an input, and control is performed so that when the pMOS transistor Tp1 is turned ON, the pMOS transistor Tp3 is forcefully turned ON for the duration corresponding to the prescribed pulse width.
Similarly, as illustrated in FIG. 3B, for example, the gate of the pMOS transistor Tp4 is supplied with a control signal CS2 having a prescribed delay and pulse width, created through inverters I11 to I14 and a NAND gate 1 by taking the signal of the node N1 as an input, and control is performed so that when the pMOS transistor Tp2 is turned ON, the pMOS transistor Tp4 is forcefully turned ON for the duration corresponding to the prescribed pulse width.
That is, the pMOS transistors Tp3 and Tp4 provided in parallel with the cross-coupled pMOS transistors Tp1 and Tp2 are normally OFF, but are turned ON only when the respective input signals, in and /in, change state.
More specifically, when the input signal, in, changes from the low level “L” to the high level “H”, the nMOS transistor Tn1 is turned ON, but since the pMOS transistor Tp1 is small (the driving capability is small), and the pMOS transistor Tp3 is OFF, the node N1 rapidly falls from the high level “H” to the low level “L”.
Then, as the voltage at the node N1 changes, the control signal CS2 created through the inverters I11 to I14 and NAND gate 1 changes from H to L and then to H (held at the low level “L” for a prescribed length of time), and the large (large driving capability) pMOS transistor Tp4 is turned ON for the prescribed length of time, forcing the potential at the node N2 to change from the low level “L” to the high level “H”.
In this way, the prior art level converter illustrated in FIG. 3A is capable of achieving high speed operation without causing an increase in power consumption. Here, the pulse width of each of the signals CS1 and CS2 for controlling the pMOS transistors Tp3 and Tp4 is determined, for example, by the delay introduced through the multi-stage inverter circuit. Accordingly, in actual use, the number of inverter stages for introducing the delay has to be increased, resulting in the problem that the amount of circuitry increases.